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#verilog
If you wanna see me struggle with #shaders and #verilog at the same time: I have a stream for you this evening!
https://www.youtube.com/live/HSV3xF_TSqg?si=YmyPzEyXG5p8ryU1
The Spade Hardware Description Language - Spade is an open-source hardware description language (HDL) developed at Linköping... - https://hackaday.com/2025/04/13/the-spade-hardware-description-language/ #hardwaredescriptionlanguage #spadelanguage #hardware #verilog #fpga #asic #vhdl #hdl
[New Blog Post] Comparing Two Verilog CPU Implementations using EBMC https://www.philipzucker.com/td4_ebmc/ #verilog #formal
Hey all! I'm due for an (re-)introduction: I'm Jack, an engineer in the NYC area from a firmware & cybersecurity background, currently working in something like hardware-software co-design.
Technical work is often with #rust #kicad #python #verilog #c, and in all-too-rare moments stuff like #haskell #forth #agda and #prolog
I've never been much for social media, usually preferring to keep interests local: a better-detailed #introduction to follow as I figure this out 
Learn PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @Raspberrypi. This intro covers #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS
https://www.youtube.com/watch?v=wWdvuAQXeS0
PipelineC aims to make 
Today's #AdventOfCode part1 was again a surprisingly fast success (anonymous variables in #perl ftw) in private leaderboard, but also weirdly easy which is _always_ a red flag for part2. I'll come back to that later, but meanwhile will make a hardware design for the number generator (#verilog), and will also have the 10yo learn how to solve it (#python). Thanks a lot to @ericwastl for not ruining Sunday with a 3d falling grid problem!
Did You Know YoSys Knows VHDL Too? - We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while... - https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/ #verilog #yosys #fpga #vhdl
First steps completed on this years #AdventOfCode pure-hardware challenge (no processor, no software) solution: behavioural #verilog that solves both parts of day 1.
Next step is to implement a hardware bubblesort with registers and a counter, then will replace behavioural model by RTL. I'm not likely to actually get it working on an #fpga ... but I am stupid enough to try.
The #Verilog source for all four dev boards and Verilator simulation is available on GitHub under the MIT licence: https://github.com/projf/projf-explore/tree/main/graphics/fpga-graphics
Is it possible to multiply a clock in a Verilog testbench? It absolutely does not need to be synthesizable, this is purely for simulation
I can generate clocks of different frequencies with "always begin" + delays but I want to guarantee an edge alignment or a phase shift
Boosts for visibility appreciated!
#verilog #fpga #hardware #openhardware
Here's the first thing I've been doing: learning Verilog and how FPGAs work. I got a Nandland Go Board a few years back and finally went through the tutorials and the creator's FPGA book. Now I understand things like clocks and signals and digital logic a lot more!
Tiny Tapeout 4: A PWM clone of Covox Speech Thing - Tiny Tapout is an interesting project, leveraging the power of cloud computing and... - https://hackaday.com/2024/06/21/tiny-tapeout-4-a-pwm-clone-of-covox-speech-thing/ #retrocomputing #githubactions #tinytapeout #synthesis #testbench #hardware #verilog #audio #asic #fpga #dac #pwm
The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are #Assembler, #Forth and #Verilog on #FPGA. I am the author of #Mecrisp, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with @BrunoLevy01 (#FemtoRV Gracilis) and I love #sizecoding challenges (Byte-Athlon Champion in #Lovebyte 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.
Well after 14 years I'm laid off from Viavi. This has been a particular nightmare for me for 14 years since I was a victim of the 2008 financial meltdown and laid off then and couldn't find work for all of 2009. It was rough.
But anyway, locally fantastic staff and great people to work with. Higher management, no comment as I am negatively biased. We made some cool stuff and I will miss seeing how my current baby will turn out.
Anyhow I don't really know how far this might go, but if someone is looking for a #EE with 25 years experience in digital design primarily with #FPGA and #VHDL (and a smattering of #Verilog), including verification mainly using #OSVVM and #UVVM (the latter modeled after #UVM) please contact me, especially if you can support remote work. I do have a professional office at home, it can be YOURS (along with me of course).
(And if so inclined, boosting this for greater visibility in networks is greatly appreciated.)